Asynchronous embedded static random access memory (SRAM) is a common memory device that requires refreshing of its memory cells to retain stored data. Embedded SRAM memory cells are typically composed of devices that hold data without having to refresh individual cells. However, the cells must have a complete electrical path to avoid a state that may cause loss of data integrity. Rather than refreshing on a periodic basis, which decreases the time during which a memory may be accessed, refreshes of the memory cells are typically performed only during a read operation during which the memory cells are read and a complete electrical path is maintained to enable the memory to retain the data.
A typical memory array includes eight word rows and multiple base two columns. The row is first selected and then the column is selected to cause the data from a particular memory cell to be addressed and refreshed by maintaining a complete electrical path. However, a circuit design using memory may not require an entire full base two range of columns or blocks or all the possible memory addresses in a row. Power conservation and gate efficiency is an important factor in circuit design and, thus, it is desirable to eliminate unnecessary memory capacity. For example, in the case of ASIC standard 2 port memory, users may configure the word length, bit length and x-y ratio by entering a desired memory length resulting in odd numbers of word lengths. When the addresses of words are not used, they are referenced as a global out of range in the case of an unused column address or a local out of range in the case of unused row addresses. For example, if a memory only requires 72 words, there would be nine full columns each having a four bit address, but seven potential block addresses would be not used and, thus, are possible global out of range addresses.
To read data from each cell, an address is sent to various row bit lines and column select lines that allow a particular word to be read. However, the cells must be refreshed during any read request because there is no scheduled refresh of the memory cells. In the case of a read directed to either a local or global out of bounds address (e.g., an attempt to access blocks 9-15 in the above example), the read would result in not refreshing the memory because the appropriate column would not exist, thereby breaking the complete electrical path and resulting in a bit line floating in a tristate condition and destroying stored data.
Thus, to insure that the memory array is refreshed whenever an out of range address is received the words in an existing row or column must be addressed to refresh the memory. The logic to determine the out of range address and refresh the appropriate existing memory blocks requires additional gates (e.g., out of range detection logic) and increases power consumption. In certain cases, access time to the memory is also increased because of the complexity of the out of range detection logic. Further, drive conflicts may occur because of propagation delay causing interference with subsequent read requests.